12471 results (0.190 seconds)

CVSS: 5.7EPSS: 0%CPEs: -EXPL: 0

13 May 2025 — Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient execution in the indirect branch predictors for some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access. • https://intel.com/content/www/us/en/security-center/advisory/intel-sa-01247.html • CWE-1423: Exposure of Sensitive Information caused by Shared Microarchitectural Predictor State that Influences Transient Execution •

CVSS: 5.7EPSS: 0%CPEs: -EXPL: 0

13 May 2025 — Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient execution for some Intel Atom(R) processors may allow an authenticated user to potentially enable information disclosure via local access. • https://intel.com/content/www/us/en/security-center/advisory/intel-sa-01247.html • CWE-1423: Exposure of Sensitive Information caused by Shared Microarchitectural Predictor State that Influences Transient Execution •

CVSS: 4.8EPSS: 0%CPEs: -EXPL: 0

13 May 2025 — Out-of-bounds read for some Intel(R) Graphics Driver software may allow an authenticated user to potentially enable information disclosure via local access. • https://intel.com/content/www/us/en/security-center/advisory/intel-sa-01253.html • CWE-125: Out-of-bounds Read •

CVSS: 5.7EPSS: 0%CPEs: 2EXPL: 0

13 May 2025 — Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution for some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access. • https://intel.com/content/www/us/en/security-center/advisory/intel-sa-01153.html • CWE-1421: Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution •

CVSS: 6.8EPSS: 0%CPEs: -EXPL: 0

13 May 2025 — Incorrect initialization of resource in the branch prediction unit for some Intel(R) Core™ Ultra Processors may allow an authenticated user to potentially enable information disclosure via local access. • https://intel.com/content/www/us/en/security-center/advisory/intel-sa-01322.html • CWE-1419: Incorrect Initialization of Resource •

CVSS: 6.0EPSS: 0%CPEs: -EXPL: 0

13 May 2025 — Exposure of sensitive information to an unauthorized actor for some Edge Orchestrator software for Intel(R) Tiber™ Edge Platform may allow an authenticated user to potentially enable information disclosure via local access. • https://intel.com/content/www/us/en/security-center/advisory/intel-sa-01239.html • CWE-200: Exposure of Sensitive Information to an Unauthorized Actor •

CVSS: 5.3EPSS: 0%CPEs: -EXPL: 0

13 May 2025 — Improper access control for some Edge Orchestrator software for Intel(R) Tiber™ Edge Platform may allow an unauthenticated user to potentially enable information disclosure via adjacent access. • https://intel.com/content/www/us/en/security-center/advisory/intel-sa-01239.html • CWE-284: Improper Access Control •

CVSS: 5.6EPSS: 0%CPEs: -EXPL: 0

13 May 2025 — Improper initialization in the UEFI firmware for the Intel(R) Server D50DNP and M50FCP boards may allow a privileged user to potentially enable information disclosure via local access. • https://intel.com/content/www/us/en/security-center/advisory/intel-sa-01269.html • CWE-665: Improper Initialization •

CVSS: 6.9EPSS: 0%CPEs: -EXPL: 0

13 May 2025 — Exposure of sensitive information to an unauthorized actor for some Edge Orchestrator software for Intel(R) Tiber™ Edge Platform may allow an authenticated user to potentially enable information disclosure via adjacent access. • https://intel.com/content/www/us/en/security-center/advisory/intel-sa-01239.html • CWE-200: Exposure of Sensitive Information to an Unauthorized Actor •

CVSS: 5.7EPSS: 0%CPEs: -EXPL: 0

13 May 2025 — Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient execution for some Intel(R) Core™ processors (10th Generation) may allow an authenticated user to potentially enable information disclosure via local access. • https://intel.com/content/www/us/en/security-center/advisory/intel-sa-01247.html • CWE-1423: Exposure of Sensitive Information caused by Shared Microarchitectural Predictor State that Influences Transient Execution •