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CVSS: 5.5EPSS: 0%CPEs: 286EXPL: 0

Insufficient access control in protected memory subsystem for SMM for 6th, 7th, 8th and 9th Generation Intel(R) Core(TM) Processor families; Intel(R) Xeon(R) Processor E3-1500 v5 and v6 families; Intel(R) Xeon(R) E-2100 and E-2200 Processor families with Intel(R) Processor Graphics may allow a privileged user to potentially enable information disclosure via local access. Un control de acceso insuficiente en el subsistema de memoria protegida para SMM para 6th, 7th, 8th y 9th Generation Intel® Core(TM) Processor families; Intel® Xeon® Processor E3-1500 v5 y v6 families; Intel® Xeon® E-2100 y E-2200 Processor families con Intel® Processor Graphics, pueden habilitar a un usuario privilegiado para permitir potencialmente una divulgación de información por medio de un acceso local. • https://support.f5.com/csp/article/K51535953?utm_source=f5support&amp%3Butm_medium=RSS https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00254.html •

CVSS: 6.5EPSS: 0%CPEs: 298EXPL: 0

Insufficient access control in subsystem for Intel (R) processor graphics in 6th, 7th, 8th and 9th Generation Intel(R) Core(TM) Processor Families; Intel(R) Pentium(R) Processor J, N, Silver and Gold Series; Intel(R) Celeron(R) Processor J, N, G3900 and G4900 Series; Intel(R) Atom(R) Processor A and E3900 Series; Intel(R) Xeon(R) Processor E3-1500 v5 and v6 and E-2100 Processor Families may allow an authenticated user to potentially enable denial of service via local access. Un control de acceso insuficiente en el subsistema para Intel® processor graphics en 6th, 7th, 8th y 9th Generation Intel® Core(TM) Processor Families; Intel® Pentium® Processor J, N, Silver y Gold Series; Intel® Celeron® Processor J, N, G3900 y G4900 Series; Intel® Atom® Processor A y E3900 Series; Intel® Xeon® Processor E3-1500 v5 y v6 y E-2100 Processor Families, puede habilitar a un usuario autenticado para permitir potencialmente una denegación de servicio por medio de un acceso local. A flaw was found in Intel graphics hardware (GPU) where a local attacker with the ability to issue an ioctl could trigger a hardware level crash if MMIO registers were read while the graphics card was in a low-power state. This creates a denial of service situation and the GPU and connected displays will remain unusable until a reboot occurs. • http://packetstormsecurity.com/files/155375/Slackware-Security-Advisory-Slackware-14.2-kernel-Updates.html https://access.redhat.com/errata/RHSA-2020:0204 https://seclists.org/bugtraq/2019/Nov/26 https://security.netapp.com/advisory/ntap-20200320-0004 https://support.f5.com/csp/article/K73659122?utm_source=f5support&amp%3Butm_medium=RSS https://usn.ubuntu.com/4186-2 https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00260.html https://access.redhat.com/security/ • CWE-284: Improper Access Control •

CVSS: 6.0EPSS: 0%CPEs: 311EXPL: 0

Configuration of SPI Flash in platforms based on multiple Intel platforms allow a local attacker to alter the behavior of the SPI flash potentially leading to a Denial of Service. La configuración de SPI Flash, en plataformas basadas en múltiples plataformas de Intel, permite que un atacante local altere el comportamiento del flash SPI. Esto podría conducir a una denegación de servicio (DoS). • http://www.securitytracker.com/id/1040626 https://security-center.intel.com/advisory.aspx?intelid=INTEL-SA-00087&languageid=en-fr https://security.netapp.com/advisory/ntap-20180924-0004 https://support.hpe.com/hpsc/doc/public/display?docLocale=en_US&docId=emr_na-hpesbhf03867en_us • CWE-269: Improper Privilege Management •

CVSS: 7.5EPSS: 0%CPEs: 20EXPL: 2

Page table walks conducted by the MMU during virtual to physical address translation leave a trace in the last level cache of modern Intel processors. By performing a side-channel attack on the MMU operations, it is possible to leak data and code pointers from JavaScript, breaking ASLR. Los paseos de la tabla de páginas llevados a cabo por la MMU durante la traducción de la dirección virtual a física dejan un rastro en la caché de último nivel de los procesadores Intel modernos. Realizando un ataque de canal lateral en las operaciones de MMU, es posible perder datos y punteros de código de JavaScript, rompiendo la ASLR. • http://www.cs.vu.nl/~herbertb/download/papers/anc_ndss17.pdf http://www.securityfocus.com/bid/96452 https://www.vusec.net/projects/anc • CWE-200: Exposure of Sensitive Information to an Unauthorized Actor •

CVSS: 7.5EPSS: 0%CPEs: 20EXPL: 2

Page table walks conducted by the MMU during virtual to physical address translation leave a trace in the last level cache of modern AMD processors. By performing a side-channel attack on the MMU operations, it is possible to leak data and code pointers from JavaScript, breaking ASLR. Los paseos de la tabla de páginas llevados a cabo por la MMU durante la traducción de la dirección virtual a física dejan un rastro en la caché de último nivel de los procesadores AMD modernos. Realizando un ataque de canal lateral en las operaciones de MMU, es posible perder datos y punteros de código de JavaScript, rompiendo la ASLR. • http://www.cs.vu.nl/~herbertb/download/papers/anc_ndss17.pdf http://www.securityfocus.com/bid/96457 https://www.vusec.net/projects/anc • CWE-200: Exposure of Sensitive Information to an Unauthorized Actor •