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CVSS: 6.7EPSS: 0%CPEs: 664EXPL: 0

Improper conditions check in voltage settings for some Intel(R) Processors may allow a privileged user to potentially enable escalation of privilege and/or information disclosure via local access. Una comprobación de condiciones inapropiadas en la configuración de voltaje para algunos procesadores Intel(R) pueden permitir que un usuario con privilegios pueda permitir la escalada de privilegios y/o la divulgación de información a través del acceso local. • https://security.netapp.com/advisory/ntap-20191217-0001 https://support.f5.com/csp/article/K10321239?utm_source=f5support&amp%3Butm_medium=RSS https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00289.html •

CVSS: 5.3EPSS: 0%CPEs: 892EXPL: 0

Improper conditions check in multiple Intel® Processors may allow an authenticated user to potentially enable partial escalation of privilege, denial of service and/or information disclosure via local access. La verificación de condiciones inadecuadas en múltiples procesadores Intel® puede permitir a un usuario autenticado habilitar potencialmente la escalada parcial de privilegios, la denegación de servicio y / o la divulgación de información a través del acceso local. • https://security.netapp.com/advisory/ntap-20191217-0002 https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00317.html https://www.synology.com/security/advisory/Synology_SA_19_42 • CWE-754: Improper Check for Unusual or Exceptional Conditions •

CVSS: 5.5EPSS: 0%CPEs: 262EXPL: 0

Insufficient access control in protected memory subsystem for Intel(R) TXT for 6th, 7th, 8th and 9th Generation Intel(R) Core(TM) Processor Families; Intel(R) Xeon(R) Processor E3-1500 v5 and v6 Families; Intel(R) Xeon(R) E-2100 and E-2200 Processor Families with Intel(R) Processor Graphics and Intel(R) TXT may allow a privileged user to potentially enable information disclosure via local access. Un control de acceso insuficiente en el subsistema de memoria protegida para Intel® TXT de 6th, 7th, 8th y 9th Generation Intel® Core(TM) Processor Families; Intel® Xeon® Processor E3-1500 v5 y v6 Families; Intel® Xeon® E-2100 y E-2200 Processor Families con Intel® Processor Graphics y Intel® TXT, puede habilitar a un usuario privilegiado para permitir potencialmente una divulgación de información por medio de un acceso local. • https://support.f5.com/csp/article/K41556648?utm_source=f5support&amp%3Butm_medium=RSS https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00164.html •

CVSS: 4.4EPSS: 0%CPEs: 394EXPL: 0

Insufficient access control in protected memory subsystem for Intel(R) SGX for 6th, 7th, 8th, 9th Generation Intel(R) Core(TM) Processor Families; Intel(R) Xeon(R) Processor E3-1500 v5, v6 Families; Intel(R) Xeon(R) E-2100 & E-2200 Processor Families with Intel(R) Processor Graphics may allow a privileged user to potentially enable information disclosure via local access. Un control de acceso insuficiente en el subsistema de memoria protegida para Intel® SGX de 6th, 7th, 8th, 9th Generation Intel® Core(TM) Processor Families; Intel® Xeon® Processor E3-1500 v5, v6 Families; Procesador Intel® Xeon® E3-1500 v5, v6 Families; Intel® Xeon® E-2100 & E-2200 Processor Families con Intel® Processor Graphics, puede habilitar a un usuario privilegiado para permitir una divulgación de información por medio de un acceso local. • https://support.f5.com/csp/article/K73837233?utm_source=f5support&amp%3Butm_medium=RSS https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00219.html •

CVSS: 7.2EPSS: 0%CPEs: 892EXPL: 0

Insufficient memory protection in Intel(R) TXT for certain Intel(R) Core Processors and Intel(R) Xeon(R) Processors may allow a privileged user to potentially enable escalation of privilege via local access. Una protección de memoria insuficiente en Intel® TXT para ciertos procesadores Intel® Core y procesadores Intel® Xeon® puede habilitar a un usuario privilegiado para permitir una escalada de privilegios por medio de un acceso local. • https://cert-portal.siemens.com/productcert/pdf/ssa-398519.pdf https://support.f5.com/csp/article/K34425791?utm_source=f5support&amp%3Butm_medium=RSS https://support.hpe.com/hpsc/doc/public/display?docLocale=en_US&docId=emr_na-hpesbhf03971en_us https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00240.html • CWE-119: Improper Restriction of Operations within the Bounds of a Memory Buffer •