CVSS: 6.5EPSS: 0%CPEs: 252EXPL: 0CVE-2021-26341 – hw: cpu: AMD CPUs may transiently execute beyond unconditional direct branch
https://notcve.org/view.php?id=CVE-2021-26341
Some AMD CPUs may transiently execute beyond unconditional direct branches, which may potentially result in data leakage. Algunas CPUs de AMD pueden ejecutar transitoriamente más allá de las ramas directas no condicionales, lo que puede potencialmente resultar en un filtrado de datos A flaw was found in hw. This issue can cause AMD CPUs to transiently execute beyond unconditional direct branches. • http://www.openwall.com/lists/oss-security/2022/03/18/2 https://www.amd.com/en/corporate/product-security/bulletin/amd-sb-1026 https://access.redhat.com/security/cve/CVE-2021-26341 https://bugzilla.redhat.com/show_bug.cgi?id=2061703 • CWE-212: Improper Removal of Sensitive Information Before Storage or Transfer CWE-552: Files or Directories Accessible to External Parties •
CVSS: 5.6EPSS: 0%CPEs: 252EXPL: 0CVE-2021-26401 – hw: cpu: LFENCE/JMP Mitigation Update for CVE-2017-5715
https://notcve.org/view.php?id=CVE-2021-26401
LFENCE/JMP (mitigation V2-2) may not sufficiently mitigate CVE-2017-5715 on some AMD CPUs. LFENCE/JMP (mitigación V2-2) puede no mitigar suficientemente CVE-2017-5715 en algunas CPUs AMD A flaw was found in hw. The speculative execution window of AMD LFENCE/JMP mitigation (MITIGATION V2-2) may be large enough to be exploited on AMD CPUs. • http://www.openwall.com/lists/oss-security/2022/03/18/2 https://www.amd.com/en/corporate/product-security/bulletin/amd-sb-1036 https://access.redhat.com/security/cve/CVE-2021-26401 https://bugzilla.redhat.com/show_bug.cgi?id=2061700 •
CVSS: 5.5EPSS: 0%CPEs: 224EXPL: 0CVE-2021-26337
https://notcve.org/view.php?id=CVE-2021-26337
Insufficient DRAM address validation in System Management Unit (SMU) may result in a DMA read from invalid DRAM address to SRAM resulting in SMU not servicing further requests. Una comprobación insuficiente de la dirección de la DRAM en System Management Unit (SMU) puede resultar en una lectura DMA desde una dirección de la DRAM no válida a la SRAM, resultando en que la SMU no atienda más peticiones • https://www.amd.com/en/corporate/product-security/bulletin/amd-sb-1027 •