CVSS: 7.8EPSS: 0%CPEs: 362EXPL: 0CVE-2019-0124
https://notcve.org/view.php?id=CVE-2019-0124
Insufficient memory protection in Intel(R) 6th Generation Core Processors and greater, supporting TXT, may allow a privileged user to potentially enable escalation of privilege via local access. Una protección insuficiente de la memoria en Intel® 6th Generation Core Processors y superiores, compatibles con TXT, puede habilitar a un usuario privilegiado para permitir potencialmente una escalada de privilegios por medio de un acceso local. • https://support.f5.com/csp/article/K81556107?utm_source=f5support&%3Butm_medium=RSS https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00220.html •
CVSS: 7.8EPSS: 0%CPEs: 362EXPL: 0CVE-2019-0123
https://notcve.org/view.php?id=CVE-2019-0123
Insufficient memory protection in Intel(R) 6th Generation Core Processors and greater, supporting SGX, may allow a privileged user to potentially enable escalation of privilege via local access. Una protección insuficiente de la memoria en Intel® 6th Generation Core Processors y superiores, compatibles con SGX, puede habilitar a un usuario privilegiado para permitir potencialmente una escalada de privilegios por medio de un acceso local. • https://support.f5.com/csp/article/K81556107?utm_source=f5support&%3Butm_medium=RSS https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00220.html •
CVSS: 5.5EPSS: 0%CPEs: 286EXPL: 0CVE-2019-0185
https://notcve.org/view.php?id=CVE-2019-0185
Insufficient access control in protected memory subsystem for SMM for 6th, 7th, 8th and 9th Generation Intel(R) Core(TM) Processor families; Intel(R) Xeon(R) Processor E3-1500 v5 and v6 families; Intel(R) Xeon(R) E-2100 and E-2200 Processor families with Intel(R) Processor Graphics may allow a privileged user to potentially enable information disclosure via local access. Un control de acceso insuficiente en el subsistema de memoria protegida para SMM para 6th, 7th, 8th y 9th Generation Intel® Core(TM) Processor families; Intel® Xeon® Processor E3-1500 v5 y v6 families; Intel® Xeon® E-2100 y E-2200 Processor families con Intel® Processor Graphics, pueden habilitar a un usuario privilegiado para permitir potencialmente una divulgación de información por medio de un acceso local. • https://support.f5.com/csp/article/K51535953?utm_source=f5support&%3Butm_medium=RSS https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00254.html •
CVSS: 6.5EPSS: 0%CPEs: 298EXPL: 0CVE-2019-0154 – hw: Intel GPU Denial Of Service while accessing MMIO in lower power state
https://notcve.org/view.php?id=CVE-2019-0154
Insufficient access control in subsystem for Intel (R) processor graphics in 6th, 7th, 8th and 9th Generation Intel(R) Core(TM) Processor Families; Intel(R) Pentium(R) Processor J, N, Silver and Gold Series; Intel(R) Celeron(R) Processor J, N, G3900 and G4900 Series; Intel(R) Atom(R) Processor A and E3900 Series; Intel(R) Xeon(R) Processor E3-1500 v5 and v6 and E-2100 Processor Families may allow an authenticated user to potentially enable denial of service via local access. Un control de acceso insuficiente en el subsistema para Intel® processor graphics en 6th, 7th, 8th y 9th Generation Intel® Core(TM) Processor Families; Intel® Pentium® Processor J, N, Silver y Gold Series; Intel® Celeron® Processor J, N, G3900 y G4900 Series; Intel® Atom® Processor A y E3900 Series; Intel® Xeon® Processor E3-1500 v5 y v6 y E-2100 Processor Families, puede habilitar a un usuario autenticado para permitir potencialmente una denegación de servicio por medio de un acceso local. A flaw was found in Intel graphics hardware (GPU) where a local attacker with the ability to issue an ioctl could trigger a hardware level crash if MMIO registers were read while the graphics card was in a low-power state. This creates a denial of service situation and the GPU and connected displays will remain unusable until a reboot occurs. • http://packetstormsecurity.com/files/155375/Slackware-Security-Advisory-Slackware-14.2-kernel-Updates.html https://access.redhat.com/errata/RHSA-2020:0204 https://seclists.org/bugtraq/2019/Nov/26 https://security.netapp.com/advisory/ntap-20200320-0004 https://support.f5.com/csp/article/K73659122?utm_source=f5support&%3Butm_medium=RSS https://usn.ubuntu.com/4186-2 https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00260.html https://access.redhat.com/security/ • CWE-284: Improper Access Control •
CVSS: 6.5EPSS: 0%CPEs: 324EXPL: 0CVE-2019-11135 – hw: TSX Transaction Asynchronous Abort (TAA)
https://notcve.org/view.php?id=CVE-2019-11135
TSX Asynchronous Abort condition on some CPUs utilizing speculative execution may allow an authenticated user to potentially enable information disclosure via a side channel with local access. Una condición de tipo TSX Asynchronous Abort en algunas CPU que utilizan ejecución especulativa puede habilitar a un usuario autenticado para permitir potencialmente una divulgación de información por medio de un canal lateral con acceso local. A flaw was found in the way Intel CPUs handle speculative execution of instructions when the TSX Asynchronous Abort (TAA) error occurs. A local authenticated attacker with the ability to monitor execution times could infer the TSX memory state by comparing abort execution times. This could allow information disclosure via this observed side-channel for any TSX transaction being executed while an attacker is able to observe abort timing. Intel's Transactional Synchronisation Extensions (TSX) are set of instructions which enable transactional memory support to improve performance of the multi-threaded applications, in the lock-protected critical sections. • http://lists.opensuse.org/opensuse-security-announce/2019-11/msg00045.html http://lists.opensuse.org/opensuse-security-announce/2019-11/msg00046.html http://lists.opensuse.org/opensuse-security-announce/2019-12/msg00042.html http://packetstormsecurity.com/files/155375/Slackware-Security-Advisory-Slackware-14.2-kernel-Updates.html http://www.openwall.com/lists/oss-security/2019/12/10/3 http://www.openwall.com/lists/oss-security/2019/12/10/4 http://www.openwall.com/lists/oss-security/2019/12 • CWE-203: Observable Discrepancy •